E2 RISC/DSP Microcontroller

The Hyperstone E2 microcontroller combines a high-performance RISC processor with a powerful DSP unit. Additional on-chip highlights include a programmable serial communication engine, an analog to digital converter (ADC), and a full 32 kBytes of on chip (I-RAM) complemented by a flexible external memory and peripheral interface controller. Maximum efficiency in terms of power consumption, gate count, and ease of programming, when utilizing RISC and DSP functionality, are inherent features of the unique Hyperstone RISC/DSP architecture.

RISC/DSP Processor Core Architecture and Instructions
Load/store architecture
96 registers organized into 64 general-purpose and 32 special-purpose registers of 32 bits each
32 global and 64 local registers of which 16 global and up to 16 local registers can be addressed directly
Instruction buffer of 128 bytes
Local registers organized in 64-word, circular register stack holding function/subroutine stack frames
Stack organized in frames comprising up to 16 words
Frames are automatically moved between memory and register stack, for fast parameter passing, the current stack frame can overlap the previous one with variable range
Fast Call and Return by parameter passing via registers
Pipelined memory access
2 stage pipeline – decode/execute – branching without wait cycles for delayed branch instructions
Variable 16, 32, and 48-Bit instructions length
Parallel execution of ALU, DSP, and load/store instructions
Most instructions execute within one cycle
Pipelined DSP instructions
Single-cycle half-word multiply-accumulate operation
Range and pointer checks are performed without any performance penalty